1. Field of the Invention
This invention relates to a semiconductor memory device, and more particularly to the technique of relieving defective bits in a static random access memory (RAM).
2. Description of the Related Art
With the development of fine pattern technology, the integration density of MOS type memory devices is further enhanced and the memory capacity has reached 1 Mbits in the static RAM. However, in this case, the rate of occurrence of defective bits resulting from dust, patterning error, crystal defects and the like caused in the manufacturing process becomes higher, lowering the manufacturing yield. Therefore, it becomes indispensable to further develop the technique of relieving the defective bits in order to solve the above problem.
The method of relieving the defective bits i attained by preparing spare memory cells and replacing defective memory cells by the spare memory cells. FIG. 1 is a block diagram of the conventional semiconductor memory device capable of relieving defective bits. Memory cells in a regular memory cell array 81 of n rows.times.m columns are selected by means of a regular row decoder 86 and a regular column decoder 87. For the regular memory cell array 81, a spare row section (spare memory cell row section) 82 of several rows or a spare column section (spare memory cell column section) 83 of several columns are provided and a spare row decoder 84 for selecting the spare row section or a spare column decoder 85 for selecting the spare column section is provided. The same address as that of the row or column in which defective bits occur can be programmed into the spare row decoder 84 or spare column decoder 85. The address programming operation is effected by blowing off a fuse connected thereto with a laser beam, for example. Further, the memory device includes a circuit (not shown) for generating a signal which inhibits the defective row or defective column of the regular memory cell array 81 from being selected in a case where the spare row section 82 or spare column section 83 is selected. With this technology, the manufacturing yield can be enhanced by replacing the row or column including the defective bits by the spare row or column.
As described above, the row or column including the defective bits may be replaced by the spare row or spare column. At this time, the row or column including the defective bits may be disconnected from the power source as shown in FIG. 2. That is, a fuse 92 is inserted between a power source line 91 of memory cells 90 and a power source Vcc, and if a defective bit occurs in at least one of the memory cells 90 connected to the power source line 90, causing a leak current, then the fuse 92 is blown off with a laser beam to disconnect the defective bit from the power source Vcc. As a result, even if a leak current occurs in the defective bit, the current can be interrupted.
In the static RAM, the memory cell 90 is constructed as shown in FIG. 3, for example. That is, the memory cell includes a first CMOS inverter IN1 which is constructed by a driving N-channel MOS transistor T1 and a load P-channel MOS transistor T3, a second CMOS inverter IN2 which is constructed by a driving N-channel MOS transistor T2 and a load P-channel MOS transistor T4, and two transfer N-channel MOS transistors T5 and T6. The output terminal and input terminal of the first CMOS inverter IN1 are respectively connected to the input terminal and output terminal of the second CMOS inverter IN2 to form a flip-flop FF. The current path of the transfer MOS transistor T5 is connected between the output terminal of the first CMOS inverter IN1 and a bit line BL. Likewise, the current path of the transfer MOS transistor T6 is connected between the output terminal of the second CMOS inverter IN2 and a bit line BL. Further, the gates of the transfer MOS transistors T5 and T6 are connected to a word line WL.
In the static RAM using the memory cell shown in FIG. 3, a through current may flow between the power sources Vcc and Vss of the memory cell only in the transient time during which the output of the flip-flop FF is being inverted. Therefore, an advantage that the current consumption in the standby mode can be suppressed to a minimum can be attained.
However, in a case where a leak current flows in at least one of a large number of memory cells of the static RAM, the current consumption in the standby mode increases even if the function of the memory cell is not affected. In this case, the above advantage cannot be attained. In order to solve this problem, a technology of interrupting the leak current occurring in the defective bit as shown in FIG. 2 can be effectively used.
Next, how the leak current occurs in the memory cell of the circuit construction shown in FIG. 3 is explained. FIG. 4 shows the cross section of a semiconductor device including the N-channel MOS transistor T1 and P-channel MOS transistor T3 constituting the CMOS inverter IN1 arranged in the memory cell of FIG. 3 formed in the silicon substrate. Element isolation regions 101 are selectively formed on the main surface of a P-type silicon substrate 100 to form element regions. The source and drain regions 102 and 103 of the N-channel MOS transistor T1 formed of N-type high impurity concentration diffusion layers are formed in the surface area of the element region of the silicon substrate 100. Further, a gate electrode 104 is formed on a gate insulation film (not shown) which is in turn disposed on a channel region formed between the source and drain regions 102 and 103. An N-well region 105 is formed in part of the silicon substrate 100. Source and drain regions 106 and 107 of P-channel MOS transistor T3 formed of P-type high impurity concentration diffusion layers are formed in the surface area of the element region of the N-well region 105. Further, a gate electrode 108 is formed on a gate insulation film (not shown) which is in turn disposed on a channel region formed between the source and drain regions 106 and 107.
The N-well region 105 and the source region 106 of the MOS transistor T3 are connected to the power source Vcc and the silicon substrate 100 and the source 102 of the MOS transistor T1 are connected to the power source Vss (ground potential). The drain regions 103 and 107 of the MOS transistors T1 and T3 are connected together by means of a wiring 109 and the gate electrodes 104 and 108 of the MOS transistors T1 and T3 are connected together by means of a wiring 110. In this case, the equivalent circuit paths for the leak current are indicated by resistors R1 to R11.
The method for interrupting the leak current explained with reference to FIG. 2 is effective for the leak current flowing through those paths R1 to R4, R6 and R7 among the leak current paths R1 to R11. However, there still remains a problem that it is impossible to interrupt the leak current caused by the N-well region 105 and flowing in the remaining leak current paths R5 and R8 to R11.